Conventionally, semiconductor memory with small cell areas to store information is used for highly-integrated large capacity memory. In this type of semiconductor memory, a plurality of bit lines is formed on the same layer of the semiconductor chip as a wiring layer.
The miniaturization of memory cells, due to the higher integration of semiconductor memory in recent years, has caused the distance between bit lines to become narrower than before. Accordingly, the parasitic capacitance between adjacent bit lines has become larger, which may cause malfunctions of the semiconductor memory.
In addition, misalignment of bit lines may cause leakage current between a contact member connected to a bit line and another adjacent bit line, thereby possibly causing malfunctions of the semiconductor memory.
Because of the misalignment of bit lines, a possibility that leakage current may occur between a contact member connected to a bit line and another adjacent bit line causing a malfunction still remains.
In addition, misalignment of a bit line and a contact member connected to the bit line may cause a leakage current between the contact member connected to the bit line and another adjacent bit line.